1. Hierarchical modeling for VLSI circuit testing
Author: / by Debashis Bhattacharya, John P. Hayes,Bhattacharya
Library: Central Library and Documents Center of Tehran University (Tehran)
Subject: Integrated Circuits -- Vey large scale integration -- Testing,Integrated Circuits -- Vey large scale integation -- Computer simulation
Classification :
TK
7874
.
B484
1990
2. LSI VLSI testability design
Author: / Frank F. Tsui,Tsui
Library: Central Library and Documents Center of Tehran University (Tehran)
Subject: Integrated Circuits -- Large scale integration -- Testing,Integrated Circuits -- Vey large scale integration -- Testing
Classification :
TH
7874
.
T78
1987
